Digital Hardware Pulse-Mode RBFNN with Hybrid On-chip Learning Algorithm Based Edge Detection.

 
 
 
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    A hardware implementation of pulse mode Radial Basis Function Neural Network (RBFNN) with on-chip learning ability is proposed in this paper. Pulse mode presents an emerging technology in digital implementation of neural networks thanks to its higher density of integration. However, hardware on-chip learning is a difficult issue, since the back-propagation algorithm is the most used, which requires a large number of logic gates in the hardware. To overcome this problem, we apply a hybrid process, which is split into two stages. In the first one, the K-means algorithm is used to update the centers of gaussian activation functions. Thereafter, the connection weights are adjusted using the back-propagation algorithm. Details of important aspects concerning the hardware implementation are given. As illustration of the efficiency and scalability of the proposed design, we consider edge detection operation which is a very important step in image processing. In the learning step, the RBFNN was taught the Canny operator behavior. Experiential results show good approximation features. The proposed design was implemented on a virtex II PRO FPGA platform and synthesis results showed higher performances when benchmarked against conventional techniques and neural ones.


 

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Article ID: 547
 
DOI: 10.14419/jacst.v2i1.547




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