Reconfigurable Architectures

Authors

  • Abida Yousuf Waza National Institute of Technology, Srinagar
  • Roohie Naaz Mir National Institute of Technology Srinagar
  • Hakim Najeeb-ud-din National Institute of Technology Srinagar

DOI:

https://doi.org/10.14419/jacst.v1i4.518

Published:

2012-11-08

Abstract

In the area of computer architecture, designers are faced with the trade-of between flexibility and performance. The architectural choices span a wide spectrum, with general-purpose processors and application specific integrated circuits (ASICs) at opposite ends. General-purpose processors are not optimized to specific applications; they are flexible due to their versatile instruction sets that allow the implementation of every computable task. ASICs are dedicated hardware devices that can achieve higher performance, require less silicon area, and are less power-consuming than instruction-level programmable processors. However, they lack in flexibility. Reconfigurable computer architectures promise to overcome this traditional trade-off and achieve both, the high performance of ASICs and the flexibility of general-purpose processors.

Author Biographies

Abida Yousuf Waza, National Institute of Technology, Srinagar

Information Technology Department

Roohie Naaz Mir, National Institute of Technology Srinagar

Computer Science and Engineering Department

Hakim Najeeb-ud-din, National Institute of Technology Srinagar

Electronics & Communication Engineering Department

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