Two Cell Fault Models and Parasitic RC Test Method for Embedded SRAM
Abstract
The existing research on two cell memory faults was not adequate to identify the current technology prone defects. The gaps in the invention of test methods and fault models in related to two-cell SRAM is lead to the development of new test techniques, that are presented in this paper. The cell size reduction in present day technologies will give effect on bit line and coupling capacitance, due to capacitive nature through coupling, each cell will get influence of its neighbouring cells, prone to the faulty behaviour. In addition, parasitic node capacitance and faulty node voltage of a defective node can induce serious parasitic effects on the electrical behaviour of SRAMs. This paper is focused on analysis of characterization of two-cell fault models using bridge or short as defect model in the electrical environment and further evaluates the necessary conditions to induce worst-case coupling effects. The proposed method guarantees detecting all two-cell faults in the presence of capacitive coupling and worst-case neighbourhood data for any possible open or short defect.
About this article
Keywords
- Two cell SRAM
- parasitic extraction
- defect induced layout
- capacitance effect
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