Diminished-1 multiplier using modulo 2n+1 adder

  • Authors

    • Beerendra Kumar Patel
    • Jitendra Kanung
    https://doi.org/10.14419/ijet.v7i4.20.22117

    Received date: November 28, 2018

    Accepted date: November 28, 2018

    Published date: November 28, 2018

  • Residue number system, computer arithmetic, diminished-1 representation, modulo 122n 1"> adders.

  • Abstract

    In this work Modulo multiplier offers higher computational speed than a normal multiplier. It is frequently used in data security and residue number system. The modulo 2n+1 has three basic blocks-partial product generation block, inverted end around carry adder tree block and diminished-1 modulo 2n+1 adder block. The result and an operand use weighted representation and others uses the diminished-1 for the modulo multiplier. The multipliers receive full inputs and avoid (n+1) bits circuits due to diminished-1 number representation. In this work, proposed modulo 2n+1 multiplier with modified diminished-1 modulo 2n+1 adder which is based on ripple carry adder. The proposed design saves significant area and power as compared to the reported one with little increment in delay.

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  • How to Cite

    Kumar Patel, B., & Kanung, J. (2018). Diminished-1 multiplier using modulo 2n+1 adder. International Journal of Engineering and Technology, 7(4.20), 31-35. https://doi.org/10.14419/ijet.v7i4.20.22117