Power analysis of single precision floating point multiplication using Vedic with proposed techniques

  • Authors

    • K V. Gowreesrinivas
    • P Samundiswary
    https://doi.org/10.14419/ijet.v7i3.29.19286

    Received date: September 9, 2018

    Accepted date: September 9, 2018

    Published date: April 20, 2026

  • Vedic, Compressor, Multiplexer, Verilog.

  • Abstract

    In design of arithmetic circuits low power consumption is one of the basic requirements in recent years. The speed of the device depends on the supply voltage degradation. In this work, a floating-point multiplication for single precision numbers using vedic with different existing techniques like full adder, 4x1 multiplexer, 3:2 compressors and proposed techniques such as modified 2x1 multiplexer moel1 and model2, modified 4:2 compressor logics XOR-MUX and XNOR-XOR-MUX logics are analyzed. The main block involved in the implementation of floating-point multiplication is 24-bit mantissa multiplier block. Further, the optimized techniques are introduced multiplier block to reduce the power dissipation. The proposed techniques such as 2x1 multiplexers, 3:2 compressor with XOR-MUX and XNOR-XOR-MUX logics and 4:2 compressor with XOR-MUX and XNOR-XOR-MUX logics for single precision floating-point multiplication provides better solution in terms of power related issues. The power analysis of single precision floating point multiplication is done and compared with the existing and modified. in terms of Power. Further, the performance metrics of vedic multiplier are analyzed for both existing and proposed techniques are compared. These floating point modules are programmed using Verilog and synthesized using Xilinx Vivado Simulator. From the simulation results, it is concluded that 4:2 compressor with XNOR-XOR-Mux logic achieves better response in terms of power.

  • References

    1. Mohan Shoba, Rangaswamy Nakkeeran, “Energy and area efficient hierarchy multiplier architecture based on Vedic mathematics and GDI logic”, International Journal of Engineering Science and Tech-nology, pp.1-11, June.2016.
    2. Irine Padma B.T and Suchitra. K, “Pipelined Floating-Point Multipli-er Based on Vedic Multiplication Technique,” International Journal of Innovative Research in Science, Engineering and Technology, Vol.3, pp.130-137, July 2014.
    3. Yashkumar. M. Warkari, Prof L.P.Thakare, Dr. A.Y. Deshmukh,”Design of Floating Point Multiplier for Fast Fourier Transform UsingVedic Sutra”, International Journal of Engineering Research and General Science, Vol.2, pp.375-382, April 2014.
    4. C.Prema,C.S.Manikandababu,”Enhanced high speed modular multi-plier using karatsuba algorithm” Proceedings of IEEE International Conference on Computer Communication and Informatics, Coimba-tore, pp.375-382, Jan 2013.
    5. A.M. Mehta, C. Bidhul, S. Joseph, and P. Jayakrishnan, “Implemen-tation of single precision floating point multiplier using karatsuba al-gorithm,” Proceedings of International Conference on Green Compu-ting, Communication and Conservation of Energy, pp.254–256, Ta-milnadu, Dec 2013.
    6. Sushma R. Huddar and Sudhir Rao, Kalpana M , Surabhi Mohan” Novel High Speed Vedic Mathematics Multiplier using Compres-sors”, Proceedings of International Conference on Communication and Signal Processing, pp.465-469, Melmaruvathur, Apr 2013.
    7. Daisuke Takahashi, “An algorithm for multiple-precision floating-point multiplication” International journal of Applied Mathematics and Computation, pp.291–298, 2005.
    8. K.Manolopoulos, D. Reisis, V.A. Chouliaras, “An efficient multiple precision floating-point Multiply-Add Fused unit”, Microelectronics Journal, pp.10–18, 2016.
    9. Peter-Michael Seidel, Guy Even, Delay-optimized implementation of IEEE floating-point addition, IEEE Trans. Comput, 53(2), February 2004.
    10. Priyanka Koneru, Tinnanti Sreenivasu, Addanki Purna Ramesh. Asynchronous Single Precision Floating Point Multiplier using Veri-log HDL, International journal of Advanced Research in Electronics and Communication Engineering, Nov 2013.
    11. Naresh Grover, MK Soni. Design of FPGA based 32-bit Floating Point Arithmetic Unit and Verification of its VHDL code using MATLAB, International Journal of Information Engineering and Electronics Business, MECS, Feb 2014.
    12. Gaurav Sharma, Arjun Singh Chauhan, Himanshu Joshi, Satish Ku-mar Alaria. Delay Comparison of 4 by 4-Vedic Multiplier based on Different Adder Architectures using VHDL, International journal of Engineering & Applied Science Research, vol.3, pp.375-381, Jun 2013.
    13. M Pravallika, V VamsiMohana Krishna. Design and Verification of High Speed and Efficient Asynchronous Floating Point Multiplier, International journal of Engineering Research and Technology, Jul 2013.
    14. Anubhuti Mittal, Ashutosh Nandi, Disha Yadav. Comparative study of 16*order FIR filter design using different multiplication tech-niques, IET Circuits, Devices & Systems, Vol.11, issue 3,pp.196-200, 2017.
    15. Hemmert, K.S., Underwood, K.D. Fast, efficient floating-point ad-ders and multipliers for FPGAs. ACM Transaction on Reconfigura-ble Technology and Systems. Vol.3, issue 3, pp. 1-11, 2010.

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  • How to Cite

    V. Gowreesrinivas, K., & Samundiswary, P. (2026). Power analysis of single precision floating point multiplication using Vedic with proposed techniques. International Journal of Engineering and Technology, 7(3.29), 443-446. https://doi.org/10.14419/ijet.v7i3.29.19286