Low Power and Low Complexity Flip-Flop Design using MIFGMOS

  • Authors

    • U Ragavendran
    • M Ramachandran
    https://doi.org/10.14419/ijet.v7i3.1.17233

    Received date: August 9, 2018

    Accepted date: August 9, 2018

    Published date: August 4, 2018

  • MIFGMOS, Flip-flop, Low power design, low-power integrated circuits, FGMOS Transistors

  • Abstract

    Sequential logic is essential in many applications as data processing for speech recognition in cochlear implants. In this paper, a family of latches based on floating-gate MOS (FGMOS) transistors is presented. This family takes advantage on the fact that FGMOS logics process data using mostly passive devices, achieving small area and low-power, requirements of modern electronics. Post-layout SPICE simulations from an ON-Semiconductors 0.5 µm CMOS process technology shows improvements over conventional CMOS logic families, making FGMOS latches ideal for low-power applications.

  • References

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  • How to Cite

    Ragavendran, U., & Ramachandran, M. (2018). Low Power and Low Complexity Flip-Flop Design using MIFGMOS. International Journal of Engineering and Technology, 7(3.1), 183-185. https://doi.org/10.14419/ijet.v7i3.1.17233