Conception and Implementation of a BCH Code on a FPGA Board

  • Authors

    • Rachid EL GOURI National School of Applied Sciences (ENSA), Ibn Tofail University P.O.Box: 242, Kenitra 14000, Morocco
    • Wassima Ait Ahmed Faculty of Sciences, Ibn Tofail University
    • Ahmed Lichioui National Society of Radio and Television (SNRT), Rabat, Morocco
    • Laamari Hlou Faculty of Sciences, Ibn Tofail University
    https://doi.org/10.14419/ijet.v2i4.1430

    Received date: October 19, 2013

    Accepted date: November 17, 2013

    Published date: November 28, 2013

  • Abstract

    In this paper we have designed and implemented a BCH (15, 7, 5) encoder on FPGA using VHDL description language and we implanted it on an FPGA Spartan 3E Starter board. The digital logic implementation of binary encoding of multiple error correcting BCH code of length n=15 is organized into shift register circuits. Multiple characteristics of cyclic codes will be discussed further on. The results of the simulation and implementation using Xilinx ISE.12.1 software and the LCD screen on the FPGA’s Board will be shown at last.

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  • How to Cite

    EL GOURI, R., Ait Ahmed, W., Lichioui, A., & Hlou, L. (2013). Conception and Implementation of a BCH Code on a FPGA Board. International Journal of Engineering and Technology, 2(4), 293-301. https://doi.org/10.14419/ijet.v2i4.1430