Design of delay efficient Booth multiplier using pipelining

  • Authors

    • Abhishek Choubey
    • SPV Subbarao
    • Shruti B. Choubey
    https://doi.org/10.14419/ijet.v7i2.16.11423

    Received date: April 12, 2018

    Accepted date: April 12, 2018

    Published date: April 12, 2018

  • Booth multiplier, Pipelining, Very-large-scale integration (VLSI).

  • Abstract

    Multiplication is one of the most an essential arithmetic operation used in numerous applications in digital signal processing and communications. These applications need transformations, convolutions and dot products that involve an enormous amount of multiplications of an operand with a constant. Typical examples include wavelet, digital filters, such as FIR or IIR. However, multiplier structures have relatively large area-delay product, long latency and significantly high power consumption compared to other the arithmetic structure. Therefore, low power multiplier design has been always a significant part of DSP structure for VLSI design. The Booth multiplier is promising as the most efficient amongst the others multiplier as it reduces the complexity of considerably than others. In this paper, we have proposed Booth-multiplier using seamless pipelining. Theoretical comparison results show that the proposed Booth multiplier requires less critical path delay compared to traditional Booth multiplier. ASIC simulation results show proposed radix-16 Booth multiplier 13% less critical path delay for word width n=16 and 17% less critical path delay compared for bit width n=32 to best existing radix-16 Booth multiplier.

  • References

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  • How to Cite

    Choubey, A., Subbarao, S., & B. Choubey, S. (2018). Design of delay efficient Booth multiplier using pipelining. International Journal of Engineering and Technology, 7(2.16), 94-96. https://doi.org/10.14419/ijet.v7i2.16.11423