To study high performance analysis of surround gate SOI MOSFET
About this article
DOI:
https://doi.org/10.14419/ijet.v7i2.8.10405Keywords:
SoiMosfet, Surround Gate, FdSoiMosfet.Abstract
In this paper, we are presenting a rigorous study about SOI MOSFET devices development. The development of SOI devices based on gate structure from single gate to surround gate is presented in this paper. We compared the various electrical characteristics between Single gate, double gate, and bulk and also discussed the device modeling based on surround gate structure.
References
H. K. Lim and J. G. Fossum, “Threshold voltage of thin-film silicon-on-insulator (SOI) MOSFETs”, IEEE Trans. Electron Devices, 1983, 30(10), 1244-1251
Colinge J.P. Thin-Film SOI Technology: The Solution to many submicron CMOS Problems IEDM dig.,(1989), 817-820
Prashant Mani, Manoj Kumar Pandey, “Silicon on Insulator MOSFET Development from Single Gate to Multiple Gate”, IJARCSSE, volume 2, Issue 6, june 2012
Prashant Mani, Shivam Sharma, “Analysis of Narrow Channel Single Gate Fully Depleted SOI MOSFET”, IJERMT, volume 2, Issue-2, March-2015
J. C. S. Woo, K. W. Terrill, and P. K. Vasudev, “Two dimensional analytic modeling of very thin SOI MOSFETs”, IEEE Trans. Electron Devices, vol.37, pp. 1999-2006, 1990
View more references (13)
C. Tinella1, F. Gianesello, D. Gloria1, C. Raynaud, P. Delatte, A. Engelstein, J.M. Fournier, Ph. Benech, J. Jomaah, “Partially Depleted CMOS SOI Technology for Low Power RF Applications,” presented at 13th GASS Symposium, Paris, 2005
L. Chang et al., “Extremely scaled silicon nano CMOS devices”, Proc. IEEE, 2003, 91(11), 1860-1873
“A Unified Analytical Fully Depleted and Partially Depleted SOI MOSFET Model”, IEEE Transactions on Electron Devices, Vol.46, No.9, pp.1872-1876,September 1999
NanditaDasGupta, AmitavaDasGupta, “Semiconductor Devices Modelling and Technology”, PHI Learning Pvt Ltd, November 2013, 305-306
J. C. S. Woo, K. W. Terill, and P. K. Vasudev, “Two dimensional analytic modeling of very thin SOI MOSFET”, IEEE Transaction on Electron Devices, vol 37, pp 1999-2006, 1990
J. P Colinge,Tyndall National Institute, “The New Generation of SOI MOSFET”, Romanian journal of information, science and technology, 11, number1, 2008, 3-15.
Sheng-Lyang Jang, Bohr Ran Huang, and Jiann-Jong Ju, “A Unified Analytical Fully Depleted and Partially Depleted SOI MOSFET Model”, IEEE Transaction on Electron Devices, Vol46, No9, pp. 1872-1876, September 1999
H.K. Lim and J. G. Fossum, “Threshold voltage of thin-film Silicon-on-Insulator (SOI) MOSFETs”, IEEE Transaction on Electron Devices, Vol. 30, pp. 1244- 1251, 1983
Prashant Mani, Manoj Kumar Pandey, “Silicon on Insulator MOSFET Development from Single Gate to Multiple Gate”, IJARCSSE, volume 2, Issue 6, june 2012
Santosh Kumar Gupta, SrimantaBaishya, “Modeling and Simulation of Triple Metal Cylindrical Surround Gate MOSFETs for Reduced Short Channel Effects”, IJSCE, Volume-2, Issue-2, May 2012.
Harikishore Kakarla, Madhavi Latha M and Habibulla Khan, “Transition Optimization in Fault Free Memory Application Using Bus-Align Mode”, European Journal of Scientific Research, Vol.112, No.2, pp.237-245, ISSN: 1450-216x135/1450-202x, October 2013.
T. Padmapriya and V. Saminadan, “Improving Throughput for Downlink Multi user MIMO-LTE Advanced Networks using SINR approximation and Hierarchical CSI feedback”, International Journal of Mobile Design Network and Innovation- Inderscience Publisher, ISSN : 1744-2850 vol. 6, no.1, pp. 14-23, May 2015.
S.V.Manikanthan and K.srividhya "An Android based secure access control using ARM and cloud computing", Published in: Electronics and Communication Systems (ICECS), 2015 2nd International Conference on 26-27Feb.2015, Publisher: IEEEDOI:10.1109, /ECS.2015.7124833.