Sapna Kumari C, Prasad KV. Analysis of power reduction and implementation on FPGA for AES-128bits using BEDT schemes. IJET [Internet]. 2017 Dec. 31 [cited 2024 Apr. 29];7(1.5):126-34. Available from: https://www.sciencepubco.com/index.php/ijet/article/view/9134