Siva Kumar M, Syed Shameem S, Raghu Sai M, Nikhil D, Kartheek P, Hari Kishore K. Efficient and low latency turbo encoder design using Verilog-Hdl. IJET [Internet]. 2017 Dec. 31 [cited 2024 Apr. 29];7(1.5):37-41. Available from: https://www.sciencepubco.com/index.php/ijet/article/view/9119