Kamar S, Fouda A, Zekry A, Elmahdy A. FPGA implementation of RS codec with interleaver in DVB-T using VHDL. IJET [Internet]. 2017 Nov. 28 [cited 2024 May 3];6(4):171-80. Available from: https://www.sciencepubco.com/index.php/ijet/article/view/8205