TOLENTINO LK, PADILLA MV, SERFA JUAN R. FPGA-based redundancy bits reduction algorithm using the enhanced error detection correction code. IJET [Internet]. 2018 Jun. 23 [cited 2024 Apr. 30];7(3):1008-13. Available from: https://www.sciencepubco.com/index.php/ijet/article/view/12681