CVS, Chaitanya, Sundaresan C, P R Venkateswaran, Keerthana Prasad, and V Siva Ramakrishna. “Design of High-Speed Multiplier Architecture Based on Vedic Mathematics”. International Journal of Engineering & Technology 7, no. 2.4 (March 10, 2018): 105–108. Accessed May 2, 2024. https://www.sciencepubco.com/index.php/ijet/article/view/11228.