Sapna Kumari, C., and K. V. Prasad. “Analysis of Power Reduction and Implementation on FPGA for AES-128bits Using BEDT Schemes”. International Journal of Engineering & Technology, vol. 7, no. 1.5, Dec. 2017, pp. 126-34, https://doi.org/10.14419/ijet.v7i1.5.9134.