[1]
R. S, H. K.M, P. R Kashyap, C. C V S, and S. C, “BCD Divider Architecture For High Speed VLSI Application Using Vedic Mathematics”, IJET, vol. 7, no. 3.29, pp. 741–743, Nov. 2018, doi: 10.14419/ijet.v7i4.29.21650.