K.R, GokulAnand; N.R, Rajalakshmi; K, Saravanan; K, Venkatachalam. Performance analysis of VLSI floor planning based on artificial bee colony algorithm. International Journal of Engineering & Technology, [S. l.], v. 7, n. 2.33, p. 755–758, 2018. DOI: 10.14419/ijet.v7i2.33.15490. Disponível em: https://www.sciencepubco.com/index.php/ijet/article/view/15490.. Acesso em: 3 may. 2024.