Noorbasha, F.; Hari Kishore, K.; Phani Sarad, P.; Renuka, A.; Meera Mohiddin, S.; Jagadeesh Babu, K.; V S. Phanindra, B.; Manasa, M. A VLSI Implementation of Train Collision Avoidance System Using Verilog HDL. IJET 2018, 7 (2.8), 386-391. https://doi.org/10.14419/ijet.v7i2.8.10468.