Operating conditions analysis of memristor model

  • Authors

    • N Khadar Basha S V University,andhra pradesh,india
    • Dr T Ramashri
    2018-09-17
    https://doi.org/10.14419/ijet.v7i4.9684
  • High Resistive State (HRS), Low Resistive State (LRS), Memristance, Nonlinear, Switching behavior.

  • The two terminal, fourth basic circuit element, memristor acts as nonlinear resistor with built-in memory functionality. Memristor has many advantages like non-volatile, no leakage current, Even when the power supply turn off, it retains its memory and typically apparent only at small scale. It shows significant effect in digital circuit application because it stores logic values without power consumption and logic values are measured based on the memristance value. Memristor is a class of non-volatile memory storage and is suitable for nanoscale memory applications. It is considered one of the most promising technology to implement memory and logic operations in a single cell. In this technology stored information is calculated as a low resistive state (LRS) and high resistive state (HRS). A detailed operating conditions of tunneling modulation model of memristor is studied and analyzed the operating frequency and voltage ranges in this paper. Switching behavior is measured based on the transition time of memristance change from one state to another state at different working frequencies.

     

     

  • References

    1. [1] L. O. Chua, “Memristor – The Missing Circuit Element,†IEEE Transactions on Circuit Theory, Vol. 18, No. 5, Pp. 507–519, 1971. https://doi.org/10.1109/TCT.1971.1083337.

      [2] L. O. Chua and S. M. Kang, “Memristive Devices and Systems,†Proceedings of the IEEE, Vol. 64, No. 2, Pp. 209–223, 1976. https://doi.org/10.1109/PROC.1976.10092.

      [3] D. B. Strukov, G. S. Snider, D. R. Stewart, and R. S. Williams, “The missing memristor found,†Nature, vol. 453, pp. 80–83, 2008. https://doi.org/10.1038/nature06932.

      [4] Y. Pershin and M. Di Ventra, Spin Memristive Systems, 2008. Arxiv preprint. [Online]. Available: http://arxiv.org/pdf/0806.2151

      [5] Y. Pershin and M. Di Ventra, “Current–voltage characteristics of semiconductor/ferromagnet junctions in the spin-blockade regime,†Phys. Rev. B, Condens. Matter, vol. 77, no. 7, p. 073301, Feb. 2008. https://doi.org/10.1103/PhysRevB.77.073301.

      [6] G. Snider, “Computing with hysteretic resistor crossbars,†Applied Physics A, vol. 80, pp. 1165–1172, 2005

      [7] S. Liu, “A new concept for non-volatile memory: The electric pulse induced resistive change effect in colossal magnetoresistive thin films,†in Proc. Non-Volatile Memory Technol. Symp., 2001, pp. 1–7.

      [8] Y. Pershin and M. Di Ventra, “Memory effects in complex materials and nanoscale systems,†Advances in Physics, vol. 60, no. 2, pp. 145–227, 2011. https://doi.org/10.1080/00018732.2010.544961.

      [9] O. Kavehei, S. Al-Sarawi, K. R. Cho, N. Iannella, S. J. Kim, K. Eshraghian, and D. Abbott, “Memristor-based synaptic networks and logical operations using in-situ computing,†in International Conference Series on Intelligent Sensors, Sensor Networks and Information Processing, ISSNIP, 2011. https://doi.org/10.1109/ISSNIP.2011.6146610.

      [10] U. Ruhrmair, C. Jaeger, M. Bator, M. Stutzmann, P. Lugli, and G. Csaba, “Applications of high-capacity crossbar memories in cryptography,†IEEE Transactions on Nanotechnology, vol. 10, no. 3, pp. 489–498, 2011. https://doi.org/10.1109/TNANO.2010.2049367.

      [11] G. Csaba and P. Lugli, “Read-out design rules for molecular crossbar architectures,†IEEE Transactions on Nanotechnology, vol. 8, no. 3, pp. 369–374, 2009. https://doi.org/10.1109/TNANO.2008.2010343.

      [12] A. Bushmaker, C. Chang, V. Deshpande, M. Amer, M. Bockrath, and S. Cronin, “Memristive behavior observed in defected single-walled carbon nanotubes,†IEEE Transactions on Nanotechnology, vol. 10, no. 3, pp. 582–586, 2011. https://doi.org/10.1109/TNANO.2010.2053717.

      [13] Y. Xia, Z. Chu, W. Hung, L.Wang, and X. Song, “An integrated optimization approach for nano-hybrid circuit cell mapping,†IEEE Transactions on Nanotechnology, 2011 .

      [14] Z. Yang, C. Ko, and S. Ramanathan, “Oxide electronics utilizing ultrafast metal-insulator transitions,†Annual Review of Materials Research, vol. 41, pp. 337–367, 2011. https://doi.org/10.1146/annurev-matsci-062910-100347.

      [15] Y. N. Joglekar and S. J. Wolf, “The elusive memristor: Properties of basic electrical circuits,†Eur. J. Phys., vol. 30, no. 4, pp. 661–675, Jul. 2009. https://doi.org/10.1088/0143-0807/30/4/001.

      [16] Z. Biolek, D. Biolek, and V. Biolkova, “SPICE model of memristor with nonlinear dopant drift,†Radioengineering, vol. 18, no. 2, pp.210–214, Jun. 2009.

      [17] D. Biolek, Z. Biolek, and V. Biolkova, “SPICE modeling of memristive, memcapacitive and meminductive systems,†in Proc. Eur. Conf.Circuit Theory Design, Aug. 2009, pp. 249–252.

      [18] A. Rak and G. Cserey, “Macromodeling of the memristor in SPICE,†IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 29, no.4, pp. 632–636, Apr. 2010. https://doi.org/10.1109/TCAD.2010.2042900.

      [19] S. Benderli and T. A.Wey, “On SPICE macromodelling of TiO2 memristors,†Electron. Lett., vol. 45, no. 7, pp. 377–379, Mar. 2009. https://doi.org/10.1049/el.2009.3511.

      [20] D. Batas and H. Fiedler, “A memristor SPICE implementation and a new approach for magnetic flux-controlled memristor modeling,†IEEE Trans. Nanotechnol., vol. 10, no. 2, pp. 250–255, Mar. 2011. https://doi.org/10.1109/TNANO.2009.2038051.

      [21] T. Prodromakis, B. P. Peh, C. Papavassiliou, and C. Toumazou, “A versatile memristor model with nonlinear dopant kinetics,†IEEE Trans. Electron Devices, vol. 58, no. 9, pp. 3099–3105, Sep. 2011. https://doi.org/10.1109/TED.2011.2158004.

      [22] C. Yakopcic, T. M. Taha, G. Subramanyam, R. E. Pino, and S. Rogers, “A memristor device model,†IEEE Electron Device Lett., vol. 32, no. 10, pp. 1436–1438, Oct. 2011. https://doi.org/10.1109/LED.2011.2163292.

      [23] C. Yakopcic, T. M. Taha, G. Subramanyam, and R. E. Pino, “Generalized memristive device SPICE model and its application in circuit design,†IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 32, no. 8, pp. 1201–1214, Aug. 2013. https://doi.org/10.1109/TCAD.2013.2252057.

      [24] A. Ascoli, R. Tetzlaff, F. Corinto, and M. Gilli, “PSpice switch-based versatile memristor model,†in Proc. IEEE Int. Symp. Circuits Syst., May 2013, pp. 205–208. https://doi.org/10.1109/ISCAS.2013.6571818.

      [25] F. Corinto and A. Ascoli, “A boundary condition-based approach to the modeling of memristor nanostructures,†IEEE Trans. Circuits Syst.I, Reg. Papers, vol. 59, no. 11, pp. 2713–2726, Nov. 2012.

      [26] Y. V. Pershin and M. Di Ventra, “SPICE model of memristive devices with threshold,†Radioengineering, vol. 22, no. 2, pp. 485–489, Jun. 2013.

      [27] Y. V. Pershin, S. La Fontaine, and M. Di Ventra, “Memristive model of amoeba learning,†Phys. Rev. E, vol. 80, no. 2, p. 021926, Aug. 2009. https://doi.org/10.1103/PhysRevE.80.021926.

      [28] P. Sheridan, K.-H. Kim, S. Gaba, T. Chang, L. Chen, and W. Lu, “Device and SPICE modeling of RRAM devices,†Nanoscale, vol. 3, no. 9, pp. 3833–3840, 2011. https://doi.org/10.1039/c1nr10557d.

      [29] X. Guan, S. Yu, and H.-S. P.Wong, “On the switching parameter variation of metal-oxide RRAM—Part I: Physical modeling and simulation methodology,†IEEE Trans. Electron Devices, vol. 59, no. 4, pp. 1172–1182, Apr. 2012. https://doi.org/10.1109/TED.2012.2184545.

  • Downloads

  • How to Cite

    Khadar Basha, N., & T Ramashri, D. (2018). Operating conditions analysis of memristor model. International Journal of Engineering & Technology, 7(4), 2291-2297. https://doi.org/10.14419/ijet.v7i4.9684