Harmonic cancellation in a Multi-level Inverter Configuration Suitable for PV Applications

  • Authors

    • Kiran Kumar Nallamekala
    • K. Venkat Raman
    • Md. Asif
    2018-09-25
    https://doi.org/10.14419/ijet.v7i4.6.20459
  • Fault tolerant inverters, Multi level- inverters, PV applications, Sine-Triangle PWM.
  • Multi-level inverters are playing a major role in PV based systems because of numerous advantages like low dv/dt, better harmonic profile so on. But, conventional multi-level inverters consist of some drawbacks like capacitor balancing issues, greater requirement of capacitor banks and clamping diodes. To address these issues, a novel multi-level inverter has been presented in this paper, which can function as a seven-level, five-level and three-level inverter. The inverter circuit utilizes six switching devices and two isolated DC voltage sources.  Moreover, when it is operated as a three-level inverter, a unipolar PWM technique is applied to the circuit which shifts all the lower order harmonics to twice of switching frequency whereas in conventional multi-level inverters, all the harmonics of lower order are present around switching frequency. In addition, proposed inverter can operate even if some switching devices of the circuit fails. Also, the behavior of the inverter during the failure of some switching devices and DC source is analyzed. The proposed inverter is simulated in MATLAB/Simulink and the results are also discussed.

     

     

  • References

    1. [1] K. Nallamekala, S. Dandabatthina and V. K. Tella, "A novel fault tolerant 21-level inverter configuration for PV applications," 2017 International Conference on Circuit ,Power and Computing Technologies (ICCPCT), Kollam, 2017, pp. 1-7.

      [2] Donald Grahame Holmes, Brendan P. McGrath “Opportunities for Harmonic Cancellation with Carrier-Based PWM for Two-Level and Multilevel Cascaded Invertersâ€, Industry Applications, IEEE Transactions on Vol. 37, No. 2, March/April 2001.

      [3] K. K. Nallamekala, M. Kalyan U and S. K, "Harmonic reduction technique with a five-level inverter for four pole induction motor drive," 2013 1st International Future Energy Electronics Conference (IFEEC), Tainan, 2013, pp. 482-487.

      [4] H. s. Patel and R. G. Haft "Generalized techniques of harmonic elimination and voltage control in thyristor inverters Part I: Harmonic elimination", IEEE Trans. Ind. Applicat vol. IA-9, pp.310 -317 1973.

      [5] J. Chatzakis, M. Vogiatzaki, H. Rigakis, M. Manitis, E. Antonidakis “novel High Bandwidth Pulse-Width Modulated Inverterâ€, Proceedings of the 10th WSEAS International Conference on CIRCUITS, Vouliagmeni, Athens, Greece, July 10-12, 2006 pp280-285.

      [6] K. K. Nallamekala, B. S. Umesh and K. Sivakumar, "A five-level inverter topology for four pole induction motor drive using four two-level inverters and two isolated DC sources," 2014 IEEE International Conference on Power Electronics, Drives and Energy Systems (PEDES), Mumbai, 2014, pp. 1-5.

      [7] Y. Takami; T. Kato; K. Inoue, "General-Purpose Computation Method of a Power Converter for Frequency Characteristics - Application to Stability Analysis of a Grid Inverter -," in IEEE Journal of Emerging and Selected Topics in Power Electronics , vol.PP, no.99, pp.1-1.

      [8] Mohan M., Renge and Hiralal M. Suryawanshi, “Five-Level Diode clamped Inverter to eliminate Common Mode Voltage and Reduced dv/dt in Medium voltage rating Induction Motor Drives,†IEEE Trans. Power Electron., vol. 23, no. 4, pp. 1598–1607, Jul. 2008.

      [9] Rodriguez, J.; Jih-Sheng Lai; Fang Zheng Peng, "Multilevel inverters: a survey of topologies, controls, and applications," IEEE Trans. Ind. Electron., vol.49, no.4, pp.724,738, Aug 2002.

      [10] Kai Tian; Bin Wu; Narimani, M.; Xu, D.D.; Zhongyuan Cheng; Reza Zargari, N., "A Capacitor Voltage-Balancing Method for Nested Neutral Point Clamped (NNPC) Inverter," in Power Electronics, IEEE Transactions on , vol.31, no.3, pp.2575-2583, March 2016.

      [11] Rabinovici, R.; Baimel, D.; Tomasik, J.; Zuckerberger, A., "Thirteen-level cascaded H-bridge inverter operated by generic phase shifted pulse-width modulation," IET Power Electron., vol.6, no.8, pp.1516,1529, September 2013.

      [12] Druant, J.; Vyncke, T.; De Belie, F.; Sergeant, P.; Melkebeek, J., "Adding Inverter Fault Detection to Model-Based Predictive Control for Flying-Capacitor Inverters," in Industrial Electronics, IEEE Transactions on , vol.62, no.4, pp.2054-2063, April 2015.

      [13] K. K. N. and K. Sivakumar, "A Quad Two-Level Inverter Configuration for Four-Pole Induction-Motor Drive with Single DC Link," in IEEE Transactions on Industrial Electronics, vol. 62, no. 1, pp. 105-112, Jan. 2015.

      [14] Nallamekala, K.K.; Sivakumar, K., "A Fault-Tolerant Dual Three-Level Inverter Configuration for Multipole Induction Motor Drive With Reduced Torque Ripple," in Industrial Electronics, IEEE Transactions on , vol.63, no.3, pp.1450-1457, March 2016.

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  • How to Cite

    Kumar Nallamekala, K., Venkat Raman, K., & Asif, M. (2018). Harmonic cancellation in a Multi-level Inverter Configuration Suitable for PV Applications. International Journal of Engineering & Technology, 7(4.6), 177-180. https://doi.org/10.14419/ijet.v7i4.6.20459