Implementation of Full Adder Using 5-Input Majority Gate

  • Authors

    • Sarvarbek Erniyazov
    • Jun Cheol Jeon
    2018-09-15
    https://doi.org/10.14419/ijet.v7i4.4.19598
  • Full-Adder, Five-Input Majority Gate, Energy Efficient, Verification.

  • In this paper full adder was created employing five-input majority gate according to Quantum-Dot Cellular Automata (QCA) innovation. We used the QCA logic in our modified structure to reduce the delay. That report details the structure furthermore investigate associated with QCA dependent 1-bit full adder design for minimal energy purposes. This method permits decreasing energy expenditure, delay, additionally location involving electronic circuits.

     

     

  • References

    1. [1] J. C. Jeon, 7-Input Majority Gate Based Priority Encoder Using Multi-Layer Quantum-Dot Cellular Automata, Advanced Science Letters. 23 (2017), 10118-10122.

      [2] N. Safoev and J.C. Jeon, Compact RCA Based on Multilayer Quantum-dot Cellular Automata, Information Systems Design and Intelligent Applications, Springer. (2018), 515-524.

      [3] J. C. Jeon and K. Y. Yoo, Elliptic Curve based Hardware Architecture using Cellular Automata, Mathematics and Computers in Simulation, 79 (2008), 1197-1203.

      [4] J. C. Jeon, Low Hardware Complexity QCA Decoding Architecture Using Inverter Chain, International Journal of Control and Automation, 9 (2016), 347-358.

      [5] R. Akeela and M. D. Wagh, A Five-input Majority Gate in Quantum-dot Cellular Automata, NSTI-Nanotech. 2 (2011), 13-16.

      [6] D. Abedi, G. Jaberipur, and M. Sangsefidi, Coplanar Full Adder in Quantum-Dot Cellular Automata via Clock-Zone-Based Crossover, IEEE Transactions on Nanotechnology, 14 (2015), 497-504.

      [7] S. Angizi1, E. Alkaldy, N. Bagherzadeh and K. Navi, Novel Robust Single Layer Wire Crossing Approach For Exclusive or Sum of Products Logic Design With Quantum-Dot Cellular Automata, Journal of Low Power Electronics, 10 (2014), 259–271.

  • Downloads

  • How to Cite

    Erniyazov, S., & Cheol Jeon, J. (2018). Implementation of Full Adder Using 5-Input Majority Gate. International Journal of Engineering & Technology, 7(4.4), 17-18. https://doi.org/10.14419/ijet.v7i4.4.19598