Scheduling and Control of Parts in FMS industry

 
 
 
  • Abstract
  • Keywords
  • References
  • PDF
  • Abstract


    This paper introduces scheduling of parts in Flexible Manufacturing System (FMS) environment by means of discrete-event simulation method. Modeling of FMS layout with 3 distinct part type, route and interval for each part is developed using Arena simulation. The ranking criterion is considered only for First-in-first-out (FIFO). Automatic Guided Vehicles (AGV) is used as a Material Handling System (MTH). In this paper a case study has been presented for effective utilization of machines and AGV in given FMS. Based on processing time for variety of parts according to their route priority the jobs are scheduled. The scheduling of the considered layout are evaluated and compared to 6 output measures which are avg. work in process (WIP), avg. queue time, avg. number of parts waiting, resource seized, machine instantaneous utilization and scheduled utilization for different replication length. The simulation outcomes are discussed in detail and conclusion has been drawn for various mentioned output measures.

     


  • Keywords


    Flexible Manufacturing system (FMS), discrete-event simulation, scheduling, FIFO, material handling system (MTH).

  • References


      [1] K.C. Jeong; Y.D.Kim (2010). A real-time scheduling mechanism for a flexible manufacturing system: Using simulation and dispatching rules, International Journal of Production Research, vol. 36, no. 9, 2609- 2626

      [2] Dr. Vijay Kumar. Mahalingam (2014).A simulation study of flexible manufacturing system using dynamic scheduling approach, Proceedings of the ASME 2014 12th Biennial Conference on Engineering Systems Design and Analysis,1-5

      [3] SZU-Yung David WU; Richard A. WYSK (2007).An application of discrete-event simulation to on-line control and scheduling in flexible manufacturing, International Journal of Production Research, VOL. 27, No.9, 1603-1623

      [4] Naveen Kumar Suniya;(2013).Analysis and Modeling of Flexible Manufacturing System Technical Report, National Institute of Technology-Rourkela

      [5] Nidhish Mathew Nidhiry; R. Saravanan(2014). FMS scheduling optimization using modified NSGA-II, International Journal of Mechanical and Production Engineering, ISSN: 2320-2092, Volume- 2, Issue- 2, 1-6

      [6] M. Abbas; A. Abbas,W.A. Khan (2016).Scheduling job shop-A case study, 14th International Symposium on Advanced Materials IOP Conf. Series: Materials Science and Engineering 146 (2016) 012052

      [7] Ankur S. Vasava (2014).Scheduling of Automated Guided Vehicle in different Flexible Manufacturing System Environment, International Journal of Innovative Research in Advanced Engineering (IJIRAE), Volume 1, Issue 8, 262-267

      [8] Muhammad Arshad; Milana Milana; Mohammed Khurshid Khan (2016).Scheduling of Three FMS Layouts Using Four Scheduling Rules, International Conference on Industrial Engineering and Operations Management, Kuala Lumpur, Malaysia, 2359-2548

      [9] T. Ravi; R.S. Lashkari; S.P. Dutta (1991). Selection of scheduling rules in FMSs- A Simulation Approach, The International Journal of Advanced Manufacturing Technology, 246-262

      [10] Dr. Gamal M. Nawara; Wael S. Hassanein,S (2013); Solving the Job-Shop Scheduling Problem by Arena Simulation Software, International Journal of Engineering Innovation & Research Volume 2, Issue 2,161-166

      [11] Pandey R; Singh A (2016), Utilization of AGVs and Machines in FMS Environment, Journal of Material Science & Engineering, Volume 5, Issue 4,1-7

      [12] Reddy B.S.P.; Rao C.S.P. (2011),Flexible Manufacturing Systems Modelling and Performance Evaluation Using AUTOMOD, It I simul model 10 (2011) 2, 78-90

      [13] J. Jerald; P. Asokan; G. Prabaharan; R. Saravanan (2004), Scheduling optimisation of flexible manufacturing systems using particle swarm optimisation algorithm, Int J Adv Manuf Technol (2005) 25: 964–971

      [14] Gaurav Kumar; Trilok Singh Bisoniya (2015),Flexible Job Shop Scheduling Operation using Genetic Algorithm, International Journal of Innovations in Engineering and Technology (IJIET), Volume 5, Issue 4, 37-41

      [15] E. Aanen; G.J. Gaalman; W.M. Nawijn (1989), PLANNING AND SCHEDULING IN AN FMS, Engineering Costs and Production Economics, 17 Elsevier Science Publishers B.V.,89-97.

      [16] Avinash Yadlapati, Dr. Hari Kishore Kakarla, “An Advanced AXI Protocol Verification using Verilog HDL”, Wulfenia Journal, ISSN: 1561-882X, Volume 22, Number 4, pp. 307-314, April 2015.

      [17] P Ramakrishna, K. Hari Kishore, “Design of Low Power 10GS/s 6-Bit DAC using CMOS Technology “International Journal of Engineering and Technology(UAE), ISSN No: 2227-524X, Vol No: 7, Issue No: 1.5, Page No: 226-229, January 2018.

      [18] A Murali, K. Hari Kishore, “Efficient and High Speed Key Independent AES Based Authenticated Encryption Architecture using FPGAs “International Journal of Engineering and Technology(UAE), ISSN No: 2227-524X, Vol No: 7, Issue No: 1.5, Page No: 230-233, January 2018.

      [19] G.S.Spandana,K Hari Kishore “A Contemporary Approach For Fault Diagnosis In Testable Reversible Circuits By Employing The CNT Gate Library” International Journal of Pure and Applied Mathematics, ISSN No: 1314-3395, Vol No: 115, Issue No: 7, Page No: 537-542, September 2017.

      [20] K Hari Kishore, CVRN Aswin Kumar, T Vijay Srinivas, GV Govardhan, Ch Naga Pavan Kumar, R Venkatesh “Design and Analysis of High Efficient UART on Spartran-6 and Virtex-7 Devices”, International Journal of Applied Engineering Research, ISSN 0973-4562, Volume 10, Number 09 , pp. 23043-23052, June 2015.

      [21] K Bindu Bhargavi, K Hari Kishore “Low Power BIST on Memory Interface Logic”, International Journal of Applied Engineering Research, ISSN 0973-4562, Volume 10, Number 08 , pp. 21079-21090, May 2015.

      [22] Korraprolu Brahma Reddy, K Hari Kishore, “A Mixed Approach for Power Dissipation Reduction in Nanometer CMOS VLSI circuits”, International Journal of Applied Engineering Research, ISSN 0973-4562 Volume 9, Number 18 , pp. 5141-5148, July 2014.

      [23] Nidamanuri Sai Charan, Kakarla Hari Kishore "Reorganization of Delay Faults in Cluster Based FPGA Using BIST” Indian Journal of Science and Technology, ISSN No: 0974-6846, Vol No.9, Issue No.28, page: 1-7, July 2016.

      [24] Sravya Kante, Hari Kishore Kakarla, Avinash Yadlapati,"Design and Verification of AMBA AHB-Lite protocol using Verilog HDL" International Journal of Engineering and Technology, E-ISSN No: 0975-4024, Vol No.8, Issue No.2, Page:734-741, May 2016.

      [25] Bandlamoodi Sravani, K Hari Kishore, “An FPGA Implementation of Phase Locked Loop (PLL)”, International Journal of Applied Engineering Research, ISSN 0973-4562, Volume 10, Number 14 , pp. 34137-34139, August 2015.

      [26] Avinash Yadlapati, Kakarla Hari Kishore,“Constrained Level Validation of Serial Peripheral Interface Protocol”, Proceedings of the First International Conference on SCI 2016, Volume 1, Smart Computing and Informatics, Smart Innovation, Systems and Technologies 77, ISSN No: 2190-3018, ISBN: 978-981-10-5544-7, Chapter No: 77, pp. 743-753, 25th December 2017.

      [27] P Kiran Kumar, P Prasad Rao, Kakarla Hari Kishore, “Optimal Design of Reversible Parity Preserving New Full Adder / Full Subtractor”, IEEE SPONSORED 3rd INTERNATIONAL CONFERENCE ON ELECTRONICS AND COMMUNICATION SYSTEMS (ICECS 2016), pp. 3465-3470, 25th and 26th February 2016.

      [28] Y Avinash, K Hari Kishore ‘’Designing Asynchronous FIFO for Low Power DFT Implementation’’ International Journal of Pure and Applied Mathematics, ISSN No: 1314-3395, Vol No: 115, Issue No: 8, Page No: 561-566, September 2017.

      [29] Mahesh Mudavathand K Hari Kishore "Design of RF Front End CMOS Cascade CS Low Noise Amplifier on 65nm Technology Process” International Journal of Pure and Applied Mathematics, ISSN No: 1314-3395, Vol No: 115, Issue No: 7, Page No: 417-422, September 2017.

      [30] P. Sahithi K Hari Kishore, E Raghuveera, P. Gopi Krishna “DESIGN OF VOLTAGE LEVEL SHIFTER FOR POWER-EFFICIENT APPLICATIONS USING 45nm TECHNOLOGY” International Journal of Engineering and Technology(UAE), ISSN No: 2227-524X, Vol No: 7, Issue No: 2.8, Page No: 103-108, March 2018.

      [31] N Bala Dastagiri K Hari Kishore “A 14-bit 10kS/s Power Efficient 65nm SAR ADC for Cardiac Implantable Medical Devices” International Journal of Engineering and Technology(UAE), ISSN No: 2227-524X, Vol No: 7, Issue No: 2.8, Page No: 34-39, March 2018.


 

View

Download

Article ID: 12034
 
DOI: 10.14419/ijet.v7i2.24.12034




Copyright © 2012-2015 Science Publishing Corporation Inc. All rights reserved.