Implementation of data path components of ARM7 microprocessor using sub threshold current mode logic with sleep transistor technique

  • Authors

    • K A. Jyotsna
    • P Satish Kumar
    • B K. Madhavi
    • Sana Bano
    2018-04-03
    https://doi.org/10.14419/ijet.v7i2.12.11292
  • ARM Processor, Current Mode Logic (CML), Leakage Currents, Sleep Transistors, Sub Threshold Logic.

  • The latest Very Large Scale Integration (VLSI) technology trends have been moving towards making devices cheaper and more powerful for everyone to afford them. So the ultimate focus being reducing power consumption by the gadgets. With the added feature of transistors to be structured in 3D, the Moore’s law is to be continued. Hence, Leakage currents are a major concern with the increasing number of transistors per chip when the technology is scaled, static power dissipation needs to be monitored. Advanced RISC Machine (ARM) Processors have been giving a new definition to smart phones, tablets and other embedded applications. This paper presents a novel technique focusing on low power technology, developing an ARM7 microprocessor using Sleep transistor with Sub threshold Current Mode Logic (STCML) technique in 45nm technology using Cadence Virtuoso Tool. The simulation results have been observed on Spectre simulator and power has been calculated in Analog Design Environment (ADE L).

     

     

  • References

    1. [1] Kanika Kaur, Arti Noor “Strategies & Methodologies for Low Power VLSI Designs: A Review†International Journal of Advances in Engineering & Technology, ISSN: 2231- 1963, vol.1, Issue 2, pp.159-165, 2011.

      [2] Bipin Gupta, Sangeeta Nakhate “Transistor Gating: A Technique for Leakage Power Reduction in CMOS Circuits†International Journal of Emerging Technology and Advanced Engineering, vol.2, Issue 4, 2010.

      [3] Md. Kamaruzzaman, Soumitra Kumar Mandal “A Novel approach for Leakage Power Reduction Techniques in CMOS VLSI Circuits†International Journal of Industrial Electronics and Electrical Engineering, vol.4, Issue 8,2016.

      [4] Vijaylaxmi C Kalal, Ravi Kumar K. I, Chaitrali V. Pawan “Novel Low Power Logic Gates using Sleepy Techniques.†International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering, vol.4, Issue 1.2015.

      [5] Sherif M. Sharroush, “Performance Optimization of MOS Current-Mode Logic†International Conference on Electrical, Electronics and Optimization Techniques, IEEE 2016, Egypt.

      [6] Yuxin Bai, Yanwei Song, Mahdi Nazm Bojnordi, Alexander Shapiro, Engin Ipek, Eby. G. Friedman “Architecting a MOS Current Mode Logic (MCML) Processor for Fast, Low Noise and Energy-Efficient Computing in the Near-Threshold Regime.†IEEE Solid state circuits, 2015.

      [7] Armin Tajalli, Elizabeth J. Brauer, Yusuf Leblebici, Eric Vittoz†Subthreshold Source Coupled Logic Circuits for Ultra-Low-Power Applications†In IEEE Journal of Solid-State Circuits, vol.43, No.7, 2008.

      [8] Rajiv Gopal, M Murali Krishna “ Subthreshold Design using SCL for Low Power Applications†International Journal of Recent Advances in Engineering & Technology. vol.2, Issue 3,2014

      [9] Steve Furber, ARM System On Chip Architecture, Addison Wesley (2000).

      [10] Enoch O. Hwang. , Digital Logic and Microprocessor Design with VHDL, Brooks/Cole (2005).

      [11] Anu Thomas, Ashly Jacob, Serin Shibu, Swathi Sudhakaran “ Comparison of Vedic Multiplier with Conventional Array and Wallace Tree Multiplier.†International Journal of VLSI Design and Communication Systems, ISSN: 2322-0929, vol.4, Issue 4, pp-0244-248, 2016.

  • Downloads

  • How to Cite

    A. Jyotsna, K., Satish Kumar, P., K. Madhavi, B., & Bano, S. (2018). Implementation of data path components of ARM7 microprocessor using sub threshold current mode logic with sleep transistor technique. International Journal of Engineering & Technology, 7(2.12), 253-256. https://doi.org/10.14419/ijet.v7i2.12.11292