Testing ripple carry adder using bist architecture

  • Authors

    • B V. Pavan Kumar
    • P Sri Ashish
    • K Sai Harshitha
    • G Sai Krishna
    • T Anil chowdary
    2018-03-18
    https://doi.org/10.14419/ijet.v7i2.7.11077
  • BIST, LFSR, MISR, Cost and Size, Signature analysis

  • Very Large-Scale Integration has a greater impact on the developing circuit technology. The Cost and Size has been gradually reducing since years but increased the circuit complexity, there are problems which may affect the growth of VLSI technology. Among them one of major problem is circuit testing. To resolve this issue, we implement Built in Self-Test (BIST). BIST architecture is used to test the circuit itself. Engineers Design BIST to achieve high reliability and low repair cycle times. We implement Linear Feedback Shift Registers (LFSR) to generate the pseudo random test pattern and implement a ripple carry adder as circuit under test and Multiple Input Signature Register(MISR) as output response analyzer and test patterns are given to circuit under test and outputs are obtained these are compared with the actual outputs to test whether the circuit is faulty or not. To check whether the circuit is faulty or fault free we check the obtained outputs with actual outputs using Signature Analysis.

     

  • References

    1. [1] Susha C Baby,Denna Markose,Lincy George, “Implementation of BIST Structure using VERILOG for VLSI Circuits,†Third national Conference on Modern Trends in Electronic Communications & Signal processing 2013.

      [2] Pushpraj Singh Tanwar,Priyanka Shrivastava, “VHDL Implementation of Logic BIST(Built In Self Test) Architecture for Multiplier Circuit for High Test Coverage in VLSI Chips,†International Journal of Advanced Research in Electrical,Electronics and Instrumentation Engineering, Vol. 3, Issue 11,pp. 12864-12870, November 2014.

      [3] Siddesh Gaonkar, “Design Of 8 Bit, 16 Bit And 32 Bit LFSR For PN Sequence Generation Using VHDL,†International Journal of Technical Research and Applications ,Special Issue 31,pp. 305-308,September 2015.

      [4] Mrs.Jamuna.S, Dr. V.K. Agrawal, “Implementation of BIST structure using VHDL for VLSI citcuits,†International Journal of Engineering Science and Technology(IJEST), Vol. 3 ,No. 6 ,pp. 5041-5048,June 2011.

      [5] Patel Chandrahash and C.S. Veena, “Ripple Carry Adder Design Using UniversalLogicGates,â€Research Journal of Engineering Sciences, Vol.3(11),pp. 1-5,November 2014.

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  • How to Cite

    V. Pavan Kumar, B., Sri Ashish, P., Sai Harshitha, K., Sai Krishna, G., & Anil chowdary, T. (2018). Testing ripple carry adder using bist architecture. International Journal of Engineering & Technology, 7(2.7), 834-837. https://doi.org/10.14419/ijet.v7i2.7.11077