Development of Framer/Deframer for 5Gbps JESD204B Soft IP

  • Abstract
  • Keywords
  • References
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  • Abstract

    This paper aimed to modify and redesign theJESD204B Full System of Lattice Semiconductor, particularly the TX deframer and RX framer modules used for the 3Gbps JESD204B soft IP to support the recently released 5Gbps JESD204B Soft IP. The modified full system instantiating the new 5Gbps JESD204B Soft IP had to be tested for functionality through RTL and gate simulation and tested for timing through Static Timing Analysis.


    The transaction layer’s RX framer, TX deframer, and the clock generator modules were identified to be the major blocks of the full system affected by the change in the soft IP. These were redesigned, followed by RTL and gate simulation of the full system. STA was checked through the Lattice Diamond tool. The system passed the simulation tests. Also, STA results showed that timing was still relaxed even if the lane speed was increased, ensuring that timing requirements are achieved by the device. It is recommended that the full system’s other blocks, and the testbench for the JESD204B and other soft IP products be investigated to operate at a higher clock frequency without violating the timing requirements and constraints of the ECP5 device.



  • Keywords

    JESD204B, Soft IP, FPGA, Lattice Semiconductor, RTL, converter

  • References

      [1] JEDEC. (2012). JESD204B.01 JEDEC Standard. JEDEC Solid State Technology Association.

      [2] Zarr, R. (2015). JESD204B Simplified. Retrieved from Electronic Design, Available at:

      [3] Abdallah, M., & Elkeelany, O. (2009), Simultaneous Multi-channel Data Acquisition and Storing System. In IEEE International Conference on Computing Engineering and Information, pp. 233-236.

      [4] Mahat, N., Sieng, L., & Rani, M. (2010). Asynchronous Multi-Channel ADC and DSP Processor Interface. In IEEE Asia Pacific Conference on Circuits and Systems, pp. 716-719.

      [5] Fernandes, A., Pereira, R., Sousa, J., Batista, A., Combo, A., Carvalho, B., & Varandas , C. (2011), HDL Based FPGA Interface Library for Data Acquisition and Multipurpose Real Time Algorithms. IEEE Transactions on Nuclear Science 58, 1526-1530.

      [6] Tiwari, A. (2012), A Low Power High Speed Dual Data Rate Acquisition System using FPGA. In IEEE International Conference on Communication, Information & Computing Technology (ICCICT), pp. 1-4.

      [7] Gupta, P., Kumar, N. (2011). Interfacing 16-Bit 1-MSPS CMOS ADC to FPGA Based Signal Processing Card. In IEEE World Congress on Information and Communication Technologies (WICT), pp. 1253-1258.

      [8] Calvet, D. (2008). A New Interface Technique for the Acquisition of Multiple Multi-Channel High Speed ADCs. IEEE Transactions on Nuclear Science 55, 2592-2597.

      [9] Somanathan, A., Bhan, D., Salunkhe, N., Joshi, J., & Tambe, A. (2014). Implementation and Analysis of an FPGA-Programmable SoC Interface towards Mixed-Signal Educational Platforms. In International Conference on Circuits, Systems, Communication and Information Technology Applications (CSCITA), pp. 99-104.

      [10] Sisterna, C., Segura, M., Guzzo, M., Ensinck, G., and Gil, C. (2011). FPGA implementation of an ultra-high speed ADC interface. In VII Southern Conference on Programmable Logic (SPL), pp. 161-166.

      [11] Lin, T., & Zhengou, Z. (2003), The implementation of 100MHz data acquisition based on FPGA. In Proceedings of 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, pp. 287-291.

      [12] Analog Devices. (2016, November). Quad, 10-bit, 40/65 MSPS Serial LVDS 1.8V ADC. AD9219.

      [13] Microprocessor and Microcomputer Standards Committee of the IEEE Computer Society. (1996, March). IEEE Standard for Low-Voltage Differential Signals (LVDS) for Scalable Coherent Interface (SCI). IEEE Std 1596.3-1996.

      [14] Sousa, F., Mauer, V., Duarte, N., Jasinski, R., & Pedroni, V. (2004). Taking Advantage of LVDS Input Buffers to Implement Sigma-Delta A/D Converters in FPGA. in IEEE International Symposium on Circuits and Systems, pp. 1088.

      [15] Camacho, J., Ibañez, A., Parrilla, M., & Fritsch, C. (2006). A Front-End Ultrasound Array Processor based on LVDS Analog-to-Digital Converters. IEEE Ultrasonics Symposium.

      [16] Saheb, H., Haider, S. (2014). Scalable High Speed Serial Interface for Data Converters. IEEE 2014 9th International Design and Test Symposium (IDT).

      [17] Lattice Semiconductor. (2014, June) LatticeCore JESD204B IP Core User’s Guide.

      [18] Lattice Semiconductor. (2013, December 20). JESD204B Full System Validation Design Specification.

      [19] Lattice Semiconductor. (2011, June). Lattice Diamond User Guide.

      [20] Lattice Semiconductor. (2016, February). ECP5™ and ECP5-5G™ Family. DS1044 Version 1.6.

      [21] Lattice Semiconductor. (2013, July). Memory Usage Guide for MachXO2 Devices. Technical Note TN1201.

      [22] Lattice Semiconductor Corporation. (2014, July 9). Sapphire JESD204B Full System Testbench Architecture.




Article ID: 11000
DOI: 10.14419/ijet.v7i2.11.11000

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