A novel design of high performance1-bit adder circuit at deep sub-micron technology

  • Authors

    • Venkata Rao Tirumalasetty
    • C V. Mohan Krishna
    • K Sai Sree Tanmaie
    • T Lakshmi Naveena
    • Ch Jonathan
    2017-12-21
    https://doi.org/10.14419/ijet.v7i1.1.10822
  • Hybrid logic, Power Consumption, Delay, Transistor Count, PDP.

  • In this paper, the design of hybrid 1-bit full adder circuit using both pass transistor and CMOS logic was implemented. Performance pa-rameters such as power, delay, and PDP were compared with the existing designs such as complementary pass-transistor logic, transmis-sion gate adder. At 0.4V supply at 22nm technology, the average power consumption is 1. 525 uW was found to be extremely low with moderately low delay 90. 25 ps and PDP found to be 0.137 fJ. The present implementation has very good improvement in terms of delay, power and power delay product when compared to the existing hybrid 1-bit full adders. Also the number of transistors has been reduced to 13 where as the existiing hybrid full adder circuit has 16 transistors. The proposed circuit was implemented using mentor graphics tool in 45nm, 32nm and 22nm technologies with different supply voltages.

     

     

  • References

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  • How to Cite

    Rao Tirumalasetty, V., V. Mohan Krishna, C., Sai Sree Tanmaie, K., Lakshmi Naveena, T., & Jonathan, C. (2017). A novel design of high performance1-bit adder circuit at deep sub-micron technology. International Journal of Engineering & Technology, 7(1.1), 660-663. https://doi.org/10.14419/ijet.v7i1.1.10822