Area, power and delay efficient 2-bit magnitude comparator using modified gdi technique in tanner 180nm technology

  • Authors

    • K Hari Kishore
    • K DurgaKoteswara Rao
    • G Manvith
    • K Biswanth
    • P Alekhya
    2018-03-19
    https://doi.org/10.14419/ijet.v7i2.8.10413
  • GDI(Gate Diffusion Input), Modified or Updated GDI technique, Magnitude Comparator,

  • Of late, low power configuration took shape into the mostimportant concentrations in designing the latest VLSI circuits. By considering the same at the maximum priority, another outline of two-bit GDI based Magnitude or Digital Comparator are recommended and actualized with the assistance of Modified GDI transistors. Comparators are building blocks in advanced VLSI configuration circuits. In the current patterns the necessity for occupying less area in chip and low power compact devices. In this paper we introduced another Magnitude Comparator which willutilize low power, and gives a quick results and occupying less chip area in Modified GDI technology. The modified GDI procedure dependent extent comparator has favorable position of less control utilization as for different outline parameters; few on-chip zones secured as small number of transistors are utilized in circuit configuration when related with traditional CMOS size comparator. Either of the circuits is outlined and executed utilizing Tanner EDA Tool version 16.0 at 180nm processing technologies.

  • References

    1. [1] M.M.Mano, "Digital design". Englewood Cliffs: Prentice Hall, 2003.

      [2] N. West and K. Eshraghian, “Principle of CMOS VLSI Design Reading," MA: Addison-Wesley, 1993

      [3] J.Park, H.C.Ngo, J.A. Silberman, and S.H.Dong, "470 ps 64-b parallel binary adder [for CPU chip]," Symp. VLSI Circuits Dig.Tech. Papers, 2000, pp.192-193.

      [4] S.Naflziger, "A sub-nanosecond O.S-um 64-b adder design," IEEE Int. Solid-State Circuit Con! Dig. Tech. Papers, 1996, pp.362-363.

      [5] R. Woo, S.-lLee, and H.-l Yoo, "A 670-ps 64-b adder design," IEEE Int. Symp. Circuit and Systems, vo1.1, May200, pp.28-31.

      [6] R.X. Gu and M.I.Elmarsy, "All-N-Logic high-speed true-single - phase dynamic CMOS logic," IEEE J. Solid-State Circuits, vol. 31, pp.221-229, Feb. 1996.

      [7] c.-c. Wang, C.-F. Wu and K.-C. Tsai, "1-GHz 64-b high-speed comparator using ANT dynamic logic with two-phase clocking," Proc. Inst.Elect. Eng. Com put. Digital Techn. vol. 14S, no.6, pp.433-436, Nov.1998.

      [8] S. Fuber, ARM "System Architecture, " Reading, MA: AddisonWesley,1997.

      [9] l-S. Wang and C.-S. Huang, "High-speed and low-power CMOS priority encoder," IEEE J. Solid-State Circuits, vol.3S, pp.ISIIISI4, Oct.2000.

      [10] H.-M. Lam and C.-Y.Tsui, "High-performance single clock cycle CMOS comparator," Electron. Lett. , vo1.42, no.2, pp.7S-77, Jan. 2006.

      [11] H.-. M.Lam and c.-Y. Tsui, "A MUX-based high-performance single-cycle CMOS comparator," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol.S4, no.7, pp.S91-S9S, Ju1.2007.

      [12] Douglas A Pucknell and Karam Ershranghian, "Basic VLSI Design," 3'd Edition, 200S Prentice Hall India.

      [13] IEEE Transactions on Very Large Scale Intergration (VLS!) System, Vol.lO, No.S, October, 2002.

      [14] J. P Uyemura, Circuit Design for CMOS VLSI Norwell, MA: Khuver Academic, 1992, pp. 88-129.

      [15] Vandana Choudhary and Rajesh Mehra, "2- Bit CMOS Comparator by Hybridizing PTL and Pseudo Logic," International Journal of Recent Technology and Engineering (IJRTE), ISSN: 2277-3878, Volume-2, Issue-2, May2013, pp. 29-32.

      [16] Anjuli and SatyajitAnand , "2- Bit Magnitude Comparator design using different logic styles," International Journal of Engineering Science Invention, ISSN(online):2319-6734, ISSN(Print):2319-672,Volume 2 Issue , January 2013: pp.13-24.

      [17] ArkadiyMorgenshtein, Alexander Fish, and Israel A Wagner, "Gate-Diflusion Input (GDI): A Power-Etlicient Method for Digital Combinatorial Circuits," IEEE Transactions on Very Large Scale Integration (VLSI) systems, Vol. 10, No. 5, October 2002, pp.566-581.

      [18] ArkadiyMorgenshtein, IdanShwartz and Alexander Fish, "Gate Diffusion Input (GO!) Logic in Standard CMOS Nanoscale Process," IEEE 26-th Convention of Electrical and Electronics Engineers in Israel 2010, pp. 776-780.

      [19] Kunal and Nidhi Kedia , "GDI Technique : A Power-Etlicient Method for Digital Circuit," International Journal of Advanced Electrical and Electronic Engineering (IJAEEE), ISSN(Print):2278-8948, Volume-I, Issue-3,2012, pp. 87-93.

      [20] Dr. Seetaiah Kilaru, Hari Kishore K, Sravani T, Anvesh Chowdary L, Balaji T “Review and Analysis of Promising Technologies with Respect to fifth Generation Networksâ€, 2014 First International Conference on Networks & Soft Computing, ISSN:978-1-4799-3486-7/14,pp.270-273,August2014.

      [21] Meka Bharadwaj, Hari Kishore "Enhanced Launch-Off-Capture Testing Using BIST Designs†Journal of Engineering and Applied Sciences, ISSN No: 1816-949X, Vol No.12, Issue No.3, page: 636-643, April 2017.

      [22] P Bala Gopal, K Hari Kishore, R.R Kalyan Venkatesh, P Harinath Mandalapu“An FPGA Implementation of On Chip UART Testing with BIST Techniquesâ€, International Journal of Applied Engineering Research, ISSN 0973-4562, Volume 10, Number 14 , pp. 34047-34051, August 2015

      [23] A Murali, K Hari Kishore, D Venkat Reddy "Integrating FPGAs with Trigger Circuitry Core System Insertions for Observability in Debugging Process†Journal of Engineering and Applied Sciences, ISSN No: 1816-949X, Vol No.11, Issue No.12, page: 2643-2650, December 2016.

      [24] Mahesh Mudavath, K Hari Kishore, D Venkat Reddy "Design of CMOS RF Front-End of Low Noise Amplifier for LTE System Applications Integrating FPGAs†Asian Journal of Information Technology, ISSN No: 1682-3915, Vol No.15, Issue No.20, page: 4040-4047, December 2016.

      [25] N Bala Dastagiri, Kakarla Hari Kishore "Reduction of Kickback Noise in Latched Comparators for Cardiac IMDs†Indian Journal of Science and Technology, ISSN No: 0974-6846, Vol No.9, Issue No.43, Page: 1-6, November 2016.

      [26] S Nazeer Hussain, K Hari Kishore "Computational Optimization of Placement and Routing using Genetic Algorithm†Indian Journal of Science and Technology, ISSN No: 0974-6846, Vol No.9, Issue No.47, page: 1-4, December 2016.

      [27] Meka Bharadwaj, Hari Kishore "Enhanced Launch-Off-Capture Testing Using BIST Designs†Journal of Engineering and Applied Sciences, ISSN No: 1816-949X, Vol No.12, Issue No.3, page: 636-643, April 2017.

      [28] N Bala Dastagiri,, K Hari Kishore "Analysis of Low Power Low Kickback Noise in Dynamic Comparators in Pacemakers†Indian Journal of Science and Technology, ISSN No: 0974-6846, Vol No.9, Issue No.44, page: 1-4, November 2016.

      [29] T. Padmapriya and V. Saminadan, “Distributed Load Balancing for Multiuser Multi-class Traffic in MIMO LTE-Advanced Networksâ€, Research Journal of Applied Sciences, Engineering and Technology (RJASET) - Maxwell Scientific Organization , ISSN: 2040-7459; e-ISSN: 2040-7467, vol.12, no.8, pp:813-822, April 2016.

      [30] S.V.Manikanthan and D.Sugandhi “ Interference Alignment Techniques For Mimo Multicell Based On Relay Interference Broadcast Channel †International Journal of Emerging Technology in Computer Science & Electronics (IJETCSE) ISSN: 0976-1353 Volume- 7 ,Issue 1 –MARCH 2014.

      [31] N.Prathima, K.Hari Kishore, “Design of a Low Power and High Performance Digital Multiplier Using a Novel 8T Adderâ€, International Journal of Engineering Research and Applications, ISSN: 2248-9622, Vol. 3, Issue.1, Jan-Feb., 2013.

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    Hari Kishore, K., DurgaKoteswara Rao, K., Manvith, G., Biswanth, K., & Alekhya, P. (2018). Area, power and delay efficient 2-bit magnitude comparator using modified gdi technique in tanner 180nm technology. International Journal of Engineering & Technology, 7(2.8), 222-226. https://doi.org/10.14419/ijet.v7i2.8.10413