Performance analysis of number theoretic transform-based convolution using field programmable gate array

  • Authors

    • G A.E Satish Kumar
    2018-03-19
    https://doi.org/10.14419/ijet.v7i2.8.10409
  • Convolution, Number Theoretic Transform, VHDL, Xilinx Spartan FPGA
  • This paper presents the convolution operation based on the Number Theoretic Transfom for two n=8 input sequences. The convolution of two n-point sequences using Fast Fourier Transform exhibits design complexity leading to high power consumption. The Number Theoretic Transform utilizes the matrix of modulus values to evaluate the convolution. The Number Theoretic Transform is as an integer transform which makes the design comparatively simple. The convolution based Number Theoretic Transform is developed using the Very High Speed Integrated Circuit Hardware Description language.Also the real time implementation of the proposed method is validated by the Xilinx Spartan FPGA family devices. The performance analysis of power, speed and area are evaluated and compared with 3A DSP FPGA and Virtex 6 FPGA devices.

  • References

    1. [1] R. Nagaraju, T. Chandra Prakash, A. Venkateshwarlu, “A Novel High Speed Convolution and De-convolutionAlgorithm Implementation Based on Ancient Indian Vedic Mathematicsâ€, International Journal of VLSI systems and Communication systems, vol.3, no.4, July 2015, pp: 514-517.

      [2] RaghidMorcel, MazenEzzeddine, HaithamAkkary, “FPGA-Based Accelerator for Deep Convolutional Neural Networks for the SPARK Environmentâ€, 2016 IEEE International Conference on Smart Cloud (SmartCloud), Nov 2016, DOI: 10.1109/SmartCloud.2016.31.

      [3] LamriLaouamer, “Towards a robust and fully reversible image watermarking framework based on number theoretic transformâ€, International Journal of Signal and Imaging Systems Engineering, vol.10, no.4, April 2017, pp.169 - 177

      [4] Alberto Pedrouzo-Ulloa, Juan Ram´onTroncoso-Pastoriza, and Fernando Pérez-González, “Number Theoretic Transforms for SecureSignal Processing†, IEEE Transactions on Information Forensics And Security, vol. 12, no. 5, May 2017, pp: 1125-1140.

      [5] Paulo Hugo E. S. Lima, Juliano B. Lima and Ricardo M. Campello de Souza, “Fractional Fourier, Hartley, Cosine and Sine Number-Theoretic Transforms Based on Matrix Functionsâ€, Circuits, Systems, and Signal Processing, vol.36, no.7, July 2017, pp 2893–2916.

      [6] CongyiLyu, Haoyao Chen, Xin Jiang, Peng LiandYunhui Liu, “Real-time object tracking system basedon field-programmable gate arrayand convolution neural networkâ€, International Journal of AdvancedRoboticSystems,SpecialIssue,Feb 2017, pp:1–14.

      [7] Hai Wang, Mengjun Shao, Yan Liu, and Wei Zhao, “Enhanced Efficiency 3D Convolution Based on Optimal FPGA Acceleratorâ€, IEEE Access, vol.5, April 2017, pp: 6909-6916

      [8] Mohammad Motamedi ,Philipp Gysel, and VenkateshAkella“Design space exploration of FPGA-based Deep Convolutional Neural Networksâ€,Design Automation Conference (ASP-DAC), 2016 21st Asia and South Pacific, Mar 2016, DOI: 10.1109/ASPDAC.2016.7428073.

      [9] R. Kalaivani, K. Ramash Kumar, S. Jeevananthan, “Implementation of VSBSMC plus PDIC for Fundamental Positive Output Super Lift-Luo Converter,†Journal of Electrical Engineering, Vol. 16, Edition: 4, 2016, pp. 243-258.

      [10] K. RamashKumar,â€Implementation of Sliding Mode Controller plus Proportional Integral Controller for Negative Output Elementary Boost Converter,†Alexandria Engineering Journal (Elsevier), 2016, Vol. 55, No. 2, pp. 1429-1445.

      [11] P. Sivakumar, V. Rajasekaran, K. Ramash Kumar, “Investigation of Intelligent Controllers for VaribaleSpeeed PFC Buck-Boost Rectifier Fed BLDC Motor Drive,†Journal of Electrical Engineering (Romania), Vol.17, No.4, 2017, pp. 459-471.

      [12] K. Ramash Kumar, D.Kalyankumar, DR.V.Kirbakaran†An Hybrid Multi level Inverter Based DSTATCOM Control, Majlesi Journal of Electrical Engineering, Vol. 5. No. 2, pp. 17-22, June 2011, ISSN: 0000-0388.

      [13] K. Ramash Kumar, S. Jeevananthan, “A Sliding Mode Control for Positive Output Elementary Luo Converter,†Journal of Electrical Engineering, Volume 10/4, December 2010, pp. 115-127.

      [14] K. Ramash Kumar, Dr.S. Jeevananthan,†Design of a Hybrid Posicast Control for a DC-DC Boost Converter Operated in Continuous Conduction Mode†(IEEE-conference PROCEEDINGS OF ICETECT 2011), pp-240-248, 978-1-4244-7925-2/11.

      [15] K. Ramash Kumar, Dr. S. Jeevananthan,†Design of Sliding Mode Control for Negative Output Elementary Super Lift Luo Converter Operated in Continuous Conduction Modeâ€, (IEEE conference Proceeding of ICCCCT-2010), pp. 138-148, 978-1-4244-7768-5/10.

      [16] K. Ramash Kumar, S. Jeevananthan, S. Ramamurthy†Improved Performance of the Positive Output Elementary Split Inductor-Type Boost Converter using Sliding Mode Controller plus Fuzzy Logic Controller, WSEAS TRANSACTIONS on SYSTEMS and CONTROL, Volume 9, 2014, pp. 215-228.

      [17] N. Arunkumar, T.S. Sivakumaran, K. Ramash Kumar, S. Saranya, â€Reduced Order Linear Quadratic Regulator plus Proportional Double Integral Based Controller for a Positive Output Elementary Super Lift Luo-Converter,†JOURNAL OF THEORETICAL AND APPLIED INFORMATION TECHNOLOGY, July 2014. Vol. 65 No.3, pp. 890-901.

      [18] Arunkumar, T.S. Sivakumaran, K. Ramash Kumar, “Improved Performance of Linear Quadratic Regulator plus Fuzzy Logic Controller for Positive Output Super Lift Luo-Converter,†Journal of Electrical Engineering, Vol. 16, Edition:3, 2016, pp. 397-408.

      [19] N Bala Dastagiri, K Hari Kishore "Novel Design of Low Power Latch Comparator in 45nm for Cardiac Signal Monitoringâ€, International Journal of Control Theory and Applications, ISSN No: 0974-5572, Vol No.9, Issue No.49, page: 117-123, May 2016.

      [20] T. Padmapriya and V. Saminadan, “Distributed Load Balancing for Multiuser Multi-class Traffic in MIMO LTE-Advanced Networksâ€, Research Journal of Applied Sciences, Engineering and Technology (RJASET) - Maxwell Scientific Organization, ISSN: 2040-7459; e-ISSN: 2040-7467, vol.12, no.8, pp:813-822, April 2016.

      [21] S.V.Manikanthanand V.Rama“Optimal Performance of Key Predistribution Protocol In Wireless Sensor Networks†International Innovative Research Journal of Engineering and Technology,ISSN NO: 2456-1983,Vol-2,Issue –Special –March 2017.

      [22] S.V.Manikanthan and K.Baskaran “Low Cost VLSI Design Implementation of Sorting Network for ACSFD in Wireless Sensor Networkâ€, CiiT International Journal of Programmable Device Circuits and Systems,Print: ISSN 0974 – 973X & Online: ISSN 0974 – 9624, Issue : November 2011, PDCS112011008.

      [23] K. Ramash Kumar, Dr. S. Jeevananthan,†Design of Sliding Mode Control for Negative Output Elementary Super Lift Luo Converter Operated in Continuous Conduction Modeâ€, (IEEE conference Proceeding of ICCCCT-2010), pp. 138-148, 978-1-4244-7768-5/10.

  • Downloads

  • How to Cite

    A.E Satish Kumar, G. (2018). Performance analysis of number theoretic transform-based convolution using field programmable gate array. International Journal of Engineering & Technology, 7(2.8), 204-210. https://doi.org/10.14419/ijet.v7i2.8.10409