Efficient high throughput decoding architecture for non-binary LDPC codes

  • Authors

    • C Arul Murugan
    • B Banuselvasaraswathy
    • K Gayathree
    • M Ishwarya Niranjana
    2018-03-19
    https://doi.org/10.14419/ijet.v7i2.8.10407
  • .

  • This article, deals with efficient trellis inbuilt decoding architecture for non-binary Linear Density Parity Check (LDPC) codes. In this decoder, a bidirectional recursion is embedded to enhance the layered scheduling and decoding latency, which in turn is used to minimize the number of iterations compared to existing techniques. Consequently, it is necessary to increase the throughput for improving the efficiency of the system. In addition, a compression technique is implemented for reducing the requirements of memory and the area. Trellis based decoder was used to reinforce the check node processing. The proposed decoder for LDPC codes yields high throughput when compared to other similar decoders presented in preceding works. The designed architecture was implemented using Cadence Virtuoso software. This decoder provides a throughput of about 39.21 Mb/s at clock frequency of 190MHz.

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    Arul Murugan, C., Banuselvasaraswathy, B., Gayathree, K., & Ishwarya Niranjana, M. (2018). Efficient high throughput decoding architecture for non-binary LDPC codes. International Journal of Engineering & Technology, 7(2.8), 195-200. https://doi.org/10.14419/ijet.v7i2.8.10407