A 14-bit 10kS/s power efficient 65nm SAR ADC for cardiac implantable medical devices

  • Authors

    • Bala Dastagiri Nadhindla
    • K Hari Kishore
    2018-03-19
    https://doi.org/10.14419/ijet.v7i2.8.10319
  • Successive Approximation Register Analog-to-Digital Converter, ENOB, INL, DNL, Cardiac Implantable Medical Device, Comparator.

  • This brief presents a 10kS/s 14 bit 12.5 ENOB Successive Approximation Register Analog-to- Digital Converter for Cardiac Implantable Medical. For achieving power efficient operation, SAR ADC employ SAR control, a new power and noise efficient comparator topology, non- binary weighted capacitive DAC. The linearity of implemented SAR ADC is enhanced with the uniform geometry of non-binary weighted capacitive DAC.The proposed SAR ADC is implemented using 65nm CMOS technology. The latched comparator consumes a power of 2.4uW and it provides an ENOB of 12.6 at a supply voltage of 1V.The INL is between -2.7/+1.6 LSB and DNL is between -0.6/+1.4LSB. The FOM of ADC is 40fJ/conv. Step which is comparable with existing ADC topologies.

  • References

    1. [1] TIHealthTech health guide, Texas Instruments, Dallas, TX, USA, 2013.

      [2] T. Morieet al.,: A 71 dB-SNDR 50 MS/s 4.2 mW CMOS SAR ADC by SNR enhancement techniques utilizing noise, in Proc. ISSCC Dig. Tech. Papers, Feb. 2013, pp. 272–273.

      [3] H. S. Lee, D. Hodges, and P. R. Gray :A self-calibrating 15 bit CMOS A/D converter, IEEE J. Solid-State Circuits, vol. 19, no. 6, pp. 813–819, Dec. 1984.https://doi.org/10.1109/JSSC.1984.1052231.

      [4] P. Harpe, E. Cantatore, and A. von Roermund: An oversampled 12/14b SAR ADC with noise reduction and linearity enhancements achieving up to 79.1 dB SNDR, in Proc. ISSCC Dig. Tech. Papers, Feb. 2014, pp. 194–195.

      [5] W. Liu, P. Huang, and Y. Chiu: A 12-bit, 45-MS/s, 3-mW redundant successive-approximation-register analog-to-digital converter with digital calibration, IEEE J. Solid-State Circuits, vol. 46, no. 11, pp. 2661–2672, Nov. 2011.https://doi.org/10.1109/JSSC.2011.2163556.

      [6] R. Kapustaet al.: A 14b 80 MS/s SAR ADC with 73.6 dB SNDR in 65 nm CMOS, in Proc. ISSCC Dig. Tech. Papers, Feb. 2013, pp. 472–473.

      [7] D. Zhang and A. Alvandpour : Analysis and calibration of nonbinaryweighted capacitive DAC for high-resolution SAR ADCs, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 61, no. 9, pp. 666–670, Sep. 2014.

      [8] Z. Boyacigiller, B. Weir, and P. Bradshaw: An error-correcting 14b/20 μs CMOS A/D converter, in Proc. ISSCC Dig. Tech. Papers, Feb. 1981, pp. 62–63.

      [9] A. M. Krämer, E. Janssen, K. Doris, and B. Murmann,:A 14b 35 MS/s SAR ADC achieving 75 dB SNDR and 99 dB SFDR with loop-embedded input buffer in CMOS: in Proc. ISSCC Dig. Tech. Papers, Feb. 2015, pp. 284–285.

      [10] Bannon, C. P. Hurrell, D. Hummerston, and C. Lyden:An 18b 5 MS/s SAR ADC with 100.2 dB dynamic range: inProc. VLSI Symp., Jun. 2014, pp. 1–2.

      [11] B. Razavi:Design of Analog CMOS Integrated Circuits. NewYork,NY, USA: McGraw-Hill, 2001.

      [12] B. Murmann, ADC Performance Survey 1997–2015.

      [13] Zhangming Zhu, and YuhuaLiang,: A 0.6-V 38-nW 9.4-ENOB 20-kS/s SAR ADC inv0.18um- CMOS for Medical Implant Devices, IEEE Journal of solid state circuits, Vol. 62, N0-9, and September 2015.

      [14] Dai Zhang, AmeyaBhide, AtilaAlvandpour,:A 53-nW 9.1-ENOB 1-KS/s SAR ADC in 0.13um CMOS for Medical Implant Devices, IEEE Journal of solid state circuits, Vol. 47, N0-7, and July 2012

      [15] SHAIK.RAZIA, M.R.NARASINGARAO published “A Neuro computing frame work for thyroid disease diagnosis using machine learning techniques†in Scopus Indexed Journal JATIT (Journal of Theoretical and Applied Information Technology, 15th May 2017. Vol.95. No.9. Pages 1996-2005) ISSN: 1992-8645 www.jatit.org E-ISSN: 1817-3195.

      [16] SHAIK.RAZIA, M.R.NARASINGARAO published “Machine learning techniques for thyroid disease diagnosis - A review†in Scopus Indexed Journal INDJST (Indian Journal of Science and Technology, ISSN: 09746846, volume-9, Issue 28, July 2016, Article number 93705).

      [17] Dr. Seetaiah Kilaru, Hari Kishore K, Sravani T, Anvesh Chowdary L, Balaji T “Review and Analysis of Promising Technologies with Respect to fifth Generation Networksâ€, 2014 First International Conference on Networks & Soft Computing, ISSN:978-1-4799-3486-7/14,pp.270-273,August2014.

      [18] Meka Bharadwaj, Hari Kishore "Enhanced Launch-Off-Capture Testing Using BIST Designs†Journal of Engineering and Applied Sciences, ISSN No: 1816-949X, Vol No.12, Issue No.3, page: 636-643, April 2017.

      [19] P Bala Gopal, K Hari Kishore, B.PraveenKittu“An FPGA Implementation of On Chip UART Testing with BIST Techniquesâ€, International Journal of Applied Engineering Research, ISSN 0973-4562, Volume 10, Number 14 , pp. 34047-34051, August 2015.

      [20] Murali, K Hari Kishore, D Venkat Reddy "Integrating FPGAs with Trigger Circuitry Core System Insertions for Observability in Debugging Process†Journal of Engineering and Applied Sciences, ISSN No: 1816-949X, Vol No.11, Issue No.12, page: 2643-2650, December 2016.

      [21] A. Mahesh Mudavath, K Hari Kishore, D Venkat Reddy "Design of CMOS RF Front-End of Low Noise Amplifier for LTE System Applications Integrating FPGAs†Asian Journal of Information Technology, ISSN No: 1682-3915, Vol No.15, Issue No.20, page: 4040-4047, December 2016.

      [22] N Bala Dastagiri, K Hari Kishore "Novel Design of Low Power Latch Comparator in 45nm for Cardiac Signal Monitoringâ€, International Journal of Control Theory and Applications, ISSN No: 0974-5572, Vol No.9, Issue No.49, page: 117-123, May 2016.

      [23] N Bala Gopal, Kakarla Hari Kishore "Reduction of Kickback Noise in Latched Comparators for Cardiac IMDs†Indian Journal of Science and Technology, ISSN No: 0974-6846, Vol No.9, Issue No.43, Page: 1-6, November 2016.

      [24] S Nazeer Hussain, K Hari Kishore "Computational Optimization of Placement and Routing using Genetic Algorithm†Indian Journal of Science and Technology, ISSN No: 0974-6846, Vol No.9, Issue No.47, page: 1-4, December 2016.

      [25] N.Prathima, K.Hari Kishore, “Design of a Low Power and High Performance Digital Multiplier Using a Novel 8T Adderâ€, International Journal of Engineering Research and Applications, ISSN: 2248-9622, Vol. 3, Issue.1, Jan-Feb., 2013.

      [26] Harikishore Kakarla, Madhavi Latha M and Habibulla Khan, “Transition Optimization in Fault Free Memory Application Using Bus-Align Modeâ€, European Journal of Scientific Research, Vol.112, No.2, pp.237-245, ISSN: 1450-216x135/1450-202x, October 2013.

      [27] T. Padmapriya and V. Saminadan, “Improving Throughput for Downlink Multi user MIMO-LTE Advanced Networks using SINR approximation and Hierarchical CSI feedbackâ€, International Journal of Mobile Design Network and Innovation- Inderscience Publisher, ISSN : 1744-2850 vol. 6, no.1, pp. 14-23, May 2015.

      [28] S.V.Manikanthan and K.srividhya "An Android based secure access control using ARM and cloud computing†Published in: Electronics and Communication Systems (ICECS), 2015 2nd InternationalConferenceon 26-27Feb. 2015, Publisher: IEEE,https://doi.org/10.1109/ECS.2015.7124833.

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    Dastagiri Nadhindla, B., & Hari Kishore, K. (2018). A 14-bit 10kS/s power efficient 65nm SAR ADC for cardiac implantable medical devices. International Journal of Engineering & Technology, 7(2.8), 30-34. https://doi.org/10.14419/ijet.v7i2.8.10319