T, Sridhar, and Dr A. S. R Murty. “Low Power Driver Receiver Topology With Delay Optimization for on-Chip Bus Interconnects”. International Journal of Engineering and Technology 7, no. 3.29 (August 24, 2018): 180–184. Accessed February 11, 2026. https://www.sciencepubco.com/index.php/IJET/article/view/18554.