TOLENTINO, Lean Karlo, Maria Victoria PADILLA, and Ronnie SERFA JUAN. “FPGA-Based Redundancy Bits Reduction Algorithm Using the Enhanced Error Detection Correction Code”. International Journal of Engineering and Technology 7, no. 3 (June 23, 2018): 1008–1013. Accessed February 9, 2026. https://www.sciencepubco.com/index.php/IJET/article/view/12681.