Performance Analysis of FinFET based SRAM at Nano-scaled Technology nodes for Low Power High Speed IC Design - Sandha, Karmjit Singh; Singh, Simranjit (International Journal of Engineering and Technology, 2019)
This paper presents performance analysis of FinFET based SRAM in terms of delay, power and power delay product (PDP) at nano-scaled technology nodes. SRAM is generally used as memories in low powered electronics gadgets. The majority of transistors of an integrated circuits (IC) are utilized as SRAM bit cells with the percentage die occupied by this type of memory approaching 85%-90% of the total area of an ICs. As the demand for the low power high-speed devices is rising, and the emergence of Internet of Thing (IoT) devices, the need for scaled down SRAM has become essential. Since SRAM is typically constructed from traditional CMOS devices, all of the issues associated with MOSFET scaling are valid for SRAM as well. The focus of the paper is to study 6T FinFET SRAM, and evaluate the different performance metrics such as delay, power dissipation and PDP at deep-submicron technology nodes. A standard 6T FinFET SRAM cells are realized using predictive technology models (PTM) for 20, 16, 14, 10 and 7nm technology nodes. The performances these SRAM cells are evaluated and results are compared for previously stated performance parameters. It is shown in the results that 7nm FinFET SRAM cells performs better at all aspects and followed by 10, 14, 16 and 20nm technology nodes.